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automotive power data sheet rev. 1.0, 2016-06-22 tle75080-emd spi driver for enhanc ed relay control spider+ 12v
data sheet 2 rev. 1.0, 2016-06-22 tle75080-emd 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 pcb set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.2 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 idle pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 electrical characteristics control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.3 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.4 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1.5 limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.6 definition of power supply modes trans ition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.1 undervoltage on v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.2 low operating power on v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 electrical characteristics po wer supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1.1 switching resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1.2 inductive output clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1.3 maximum load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 inverse current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 switching channels in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 over temperature and over load protection in limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6 electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 over load and over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table of contents
tle75080-emd table of contents data sheet 3 rev. 1.0, 2016-06-22 9.2 output status monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.5 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.6 spi registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.1 standard diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.2 register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.6.3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.6.4 spi command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.1 further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
tle75080-emd list of figures data sheet 4 rev. 1.0, 2016-06-22 figure 1 block diagram of tle75080-emd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 pin configuration tle75080-emd in pg-ssop-24-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 2s2p pcb cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5 pc board for thermal simulation with 600 mm2 cooling ar ea . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6 pc board for thermal simulation with 2s2p cooling area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7 typical thermal impedance. pcb setup according chapter 4.3.1 . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8 typical thermal resistance. pcb setup 1s0p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 tle75080-emd internal power supp ly concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11 ?cranking operative range? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12 operation mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13 transition time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14 v s undervoltage behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15 switching a resistive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16 output clamp concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17 over load current thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18 latch off at over load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 19 restart timer in limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20 output status monitor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 21 output status monitor - concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 23 combinatorial logic for ter bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 24 daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 25 data transfer in daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 26 timing diagram spi access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 27 relationship between si and so during spi communicati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 28 register content sent back to c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29 tle75080-emd response after a error in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 30 tle75080-emd response after coming out of power-on reset at v dd . . . . . . . . . . . . . . . . . . . . . 56 figure 31 tle75080-emd response after a command syntax error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 32 tle75080-emd application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 33 pg-ssop-24-9 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 34 tle75080-emd package pads and stencil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 list of figures
tle75080-emd list of tables data sheet 5 rev. 1.0, 2016-06-22 table 1 product summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2 absolute maximum ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5 electrical characteristics: control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6 device capability as function of v s and v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7 device function in relation to operation modes, v s and v dd voltages . . . . . . . . . . . . . . . . . . . . . . 26 table 8 electrical characteristics power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9 electrical characteristics: power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 10 electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11 electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 12 electrical characteristics serial pe ripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 13 spi command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 14 standard diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 15 register structure - all registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 16 register addressing space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 17 addressable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 18 spi command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 19 suggested component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 list of tables
pg-ssop-24-9 package marking pg-ssop-24-9 TLE75080EMD data sheet 6 rev. 1.0, 2016-06-22 spi driver for enhanced relay control tle75080-emd 1overview features ? 16-bit serial peripheral inte rface for control and diagnosis ? daisy chain capability spi also co mpatible with 8-bit spi devices ? 2 cmos compatible parallel in put pins with input mapping functionality ? cranking capability down to v s = 3.0 v (supports lv124) ? digital supply voltage range compatible with 3.3 v and 5 v microcontrollers ? two independent battery feeds ( v s1 , v s2 ) for high-side channels ? very low quiescent current (with usage of idle pin) ? limp home mode (with usage of idle and in pins) ? green product (rohs compliant) ? aec qualified description the tle75080-emd is an eight channel high-side power switch in pg-ssop-24-9 package providing embedded protective functions. it is specially designed to control relays and leds in automotive and industrial applications. a serial peripheral inte rface (spi) is utilized for cont rol and diagnosis of the loads as well as of the device. for direct control and pwm there are two input pins availabl e connected to two outputs by default. additional or different outputs can be controlled by t he same input pins (programmable via spi). table 1 product summary parameter symbol values analog supply voltage v s 3.0 v ? 28 v digital supply voltage v dd 3.0 v ? 5.5 v minimum overvoltage protection v s(az) 42 v (see chapter 8.5 for details) maximum on-state resistance at t j = 150 c r ds(on) 2.2 ? nominal load current ( t a = 85 c, all channels) i l(nom) 330 ma maximum energy dissipation - repetitive e ar 10 mj @ i l(ear) = 220 ma maximum source to ground clamping voltage v out(cl) -16 v maximum overload switch off threshold i l(ovl0) 2.3 a maximum total quiescent current at t j 85 c i sleep 5a maximum spi clock frequency f sclk 5mhz
tle75080-emd overview data sheet 7 rev. 1.0, 2016-06-22 applications ? high-side switches for 12 v in automotive or industrial a pplications such as lighting, heating, motor driving, energy and power distribution ? especially designed for driving relays, leds and motors. protective functions ? reverse battery protection on v s without external components ? short circuit to ground and battery protection ? stable behavior at under voltage conditions (?lower supply voltage range for extended operation?) ? over current latch off ? thermal shutdown latch off ? overvoltage protection ? loss of ground protection ? loss of battery protection ? electrostatic discharge (esd) protection diagnostic features ? latched diagnostic information via spi register ? over load detection at on state ? open load detection at off state us ing output status monitor function ? output status monitor ? input status monitor application specific functions ? fail-safe activation via input pins in limp-home mode ? spi with daisy chain capability ? safe operation at low battery voltage (cranking) ? two supply pins for different battery feeds (each pin is the power drain of four high-side channels) detailed description the tle75080-emd is an eight channel high-side switch providing embedded protective functions. the output stages incorporate eight hi gh-side switches (typical r ds(on) at t j = 25c is 1 ? ). the 16-bit serial peripheral interface (spi) is utilized to control and diagnose the device and the loads. the spi interface provides daisy chain capability in order to assemble mu ltiple devices (also devi ces with 8 bit spi) in one spi chain by using the same number of microcontroller pins. this device is designed for low supply voltage operation, therefore being able to keep its state at low battery voltage ( v s 3.0 v). the spi functionality, in cluding the possibility to program th e device, is available only when the digital power supply is present (see chapter 6 for more details). the tle75080-emd is equipped with two input pins that are connected to tw o outputs, making them controllable even when the digital supply voltage is not available. with the input mapping functionality it is possible to connect the input pins to different outputs, or assign more outputs to the same input pin. in this case more channels can be controlled with one signal applied to one input pin.
tle75080-emd overview data sheet 8 rev. 1.0, 2016-06-22 in limp home mode (fail-safe mode) the input pins are directly routed to channel s 2 and 3. when idle pin is ?low?, it is possible to activate the two channels using th e input pins independently from the presence of the digital supply voltage. the device provides diagnosis of the l oad via open load at off state (with diag_osm.outn bits) and short circuit detection. for open load at off state detection, a internal current source i ol can be activated via spi. each output stage is protected against short circuit. in case of overload, the affe cted channel switches off when the overload detection current i l(ovln) is reached and can be reactivated via spi. in limp home mode operation, the channels connected to an input pin set to ?hig h? restart automatically af ter output restart time t retry(lh) is elapsed. temperature sensors are available for each ch annel to protect the device against over temperature. the power transistors are built by n-channel power mosf et with one central chargepump . the inputs are ground referenced ttl compatible. the device is mono lithically integrated in smart power technology.
tle75080-emd block diagram and terms data sheet 9 rev. 1.0, 2016-06-22 2 block diagram and terms 2.1 block diagram figure 1 block diagram of tle75080-emd blockdiagram _080noled.emf control, diagnostic and protective functions limp home high -side gate control in1 idle in0 power supply vs out3_hs out1_hs out2_hs csn si sclk so diagnosis register input register vdd spi power mode control out4_hs out5_hs out6_hs out7_hs output status monitor temperature sensor over load detection gnd vs 1 vs 2 out0_hs
tle75080-emd block diagram and terms data sheet 10 rev. 1.0, 2016-06-22 2.2 terms figure 2 shows all terms used in this data sheet, wit h associated convention for positive values. figure 2 voltage and current definition in all tables of electrical characteristics the channe l related symbols without channel numbers are valid for each channel separately (e.g. v ds specification is valid for v ds0 ... v ds7 ). furthermore, parameters relative to output current can be indicated without specifying whether the current is going into the drain pin or going out of the source pin, unless otherwise specified. for in stance, nominal output current can be indicated in the following ways: i l(nom) i l_hs(nom) i l_s(nom) all spi registers bits are marked as follows: addr.parameter (e.g. hwcr.rst ) with the exception of the bits in the diagnosis frames which are marked only with parameter (e.g. uvrvs ). terms_8hs.emf v in 1 v s v so i vd d i si i csn i vs vdd idle si csn vs in1 i sc l k sclk i in 0 in0 i id l e so gnd i gnd vs1 vs2 v si v sc l k v csn v in 0 v id l e v dd i vs 2 v s2 i vs1 v s1 i so i in 1 out2_hs out4_hs out6_hs i l_s6 i l_s4 i l_s2 out0_hs i l_s0 out1_hs out3_hs out5_hs out7_hs i l_s7 i l_s5 i l_s3 i l_s1 v ds0 v out0 v ds2 v out2 v ds4 v out4 v ds6 v out6 v ds1 v out1 v ds3 v out3 v ds5 v out5 v ds7 v out7
tle75080-emd pin configuration data sheet 11 rev. 1.0, 2016-06-22 3 pin configuration 3.1 pin assignment figure 3 pin configuration tle75080-emd in pg-ssop-24-9 pinout_8hs.emf (top view) vdd in0 in1 idle vs out1_hs out2_hs vs1 out4_hs out6_hs csn sclk si so gnd out0_hs out3_hs vs2 out5_hs out7_hs 18 17 16 15 14 13 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 25 sub exposed pad (bott om) n.c. n.c. n.c. n.c.
tle75080-emd pin configuration data sheet 12 rev. 1.0, 2016-06-22 3.2 pin definitions and functions pin symbol i/o function power supply pins 20 vs ? analog supply v s positive supply voltage for power swit ches gate control (incl. protections) 9 vs1 ? analog supply v s1 positive supply voltage for power swit ches drain current (channels 0, 2, 4 and 6) 16 vs2 ? analog supply v s2 positive supply voltage for power swit ches drain current (channels 1, 3, 5 and 7) 24 vdd ? digital supply v dd supply voltage for spi wit h support function to v s 5gnd? ground ground connection spi pins 1csni chip select ?low? active, integrated pull-up to v dd 2sclki serial clock ?high? active, integrated pull-down to ground 3sii serial input ?high? active, integrated pull-down to ground 4soo serial output ?z? (tri-state) when csn is ?high? input and stand-by pins 21 idle i idle mode power mode control, ?high? activates idle mode, integrated pull-down to ground 23 in0 i input pin 0 connected to channel 2 by default and in limp home mode, ?high? active, integrated pull-down to ground 22 in1 i input pin 1 connected to channel 3 by default and in limp home mode, ?high? active, integrated pull-down to ground power ouput pins 6 out0_hs o source of high-side power transistor (channel 0) 8 out2_hs o source of high-side power transistor (channel 2) 10 out4_hs o source of high-side power transistor (channel 4) 11 out6_hs o source of high-side power transistor (channel 6) 14 out7_hs o source of high-side power transistor (channel 7) 15 out5_hs o source of high-side power transistor (channel 5) 17 out3_hs o source of high-side power transistor (channel 3)
tle75080-emd pin configuration data sheet 13 rev. 1.0, 2016-06-22 19 out1_hs o source of high-side power transistor (channel 1) not connected pins / cooling tab 7, 12, 13, 18 n.c. ? not connec ted, internally not bonded 25 gnd ? exposed pad it is recommended to connect it to pcb ground for cooling and emc - not usable as electrical gnd pin. electrical ground must be provided by pin 5. pin symbol i/o function
tle75080-emd general product characteristics data sheet 14 rev. 1.0, 2016-06-22 4 general product characteristics 4.1 absolute maximum ratings table 2 absolute maximum ratings 1) t j = -40 c to +150 c all voltages with respect to ground, positive curr ent flowing into pin (unless otherwise specified) voltage ranges specifed for v s apply also to v s1 and v s2 (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. supply voltages analog supply voltage v s -0.3 ? 28 v ? p_4.1.1 digital supply voltage v dd -0.3 ? 5.5 v ? p_4.1.2 supply voltage for load dump protection v s(ld) ??42v 2) p_4.1.3 supply voltage for short circuit protection (single pulse) v s(sc) 0?28v? p_4.1.4 reverse polarity voltage -v s(rev) ??16v 3) t j(0) = 25 c t 2 min see chapter 11 for general setup. r l =70 ? on all channels p_4.1.5 current through vs pin i vs -10 ? 10 ma t 2 min p_4.1.7 current through vdd pin i vdd -50 ? 10 ma t 2 min p_4.1.8 power stages load current | i l |?? i l(ovl0) a single channel p_4.1.9 voltage at power transistor v ds -0.3 ? 42 v ? p_4.1.10 power transistor source voltage v out_s -16 ? v out_d +0.3 v? p_4.1.11 power transistor drain voltage ( v out_s 0v) v out_d v out_s -0.3 ?42 v ? p_4.1.12 power transistor drain voltage ( v out_s < 0 v) v out_d -0.3 ? 42 v ? p_4.1.59 maximum energy dissipation single pulse e as ??50mj 4) t j(0) = 25 c i l(0) = 2* i l(ear) p_4.1.13 maximum energy dissipation single pulse e as ??25mj 4) t j(0) = 150 c i l(0) = 400 ma p_4.1.14
tle75080-emd general product characteristics data sheet 15 rev. 1.0, 2016-06-22 maximum energy dissipation repetitive pulses - i l(ear) e ar ??10mj 4) t j(0) = 85 c i l(0) = i l(ear) 2*10 6 cycles p_4.1.15 idle pin voltage at idle pin v idle -0.3 5.5 v ? p_4.1.23 current through idle pin i idle -0.75 0.75 ma ? p_4.1.25 current through idle pin i idle -10.0 2.0 ma t 2min. p_4.1.26 input pins voltage at input pins v in -0.3 5.5 v ? p_4.1.28 current through input pins i in -0.75 0.75 ma ? p_4.1.30 current through input pins i in -10.0 2.0 ma t 2min. p_4.1.31 spi pins voltage at chip select pin v csn -0.3 5.5 v ? p_4.1.33 current through chip select pin i csn -0.75 0.75 ma ? p_4.1.34 current through chip select pin i csn -10.0 2.0 ma t 2min. p_4.1.35 voltage at serial clock pin v sclk -0.3 5.5 v p_4.1.37 current through serial clock pin i sclk -0.75 0.75 ma ? p_4.1.38 current through serial clock pin i sclk -10.0 2.0 ma t 2min. p_4.1.39 voltage at serial input pin v si -0.3 5.5 v p_4.1.41 current through serial input pin i si -0.75 0.75 ma ? p_4.1.42 current through serial input pin i si -10.0 2.0 ma t 2min. p_4.1.43 voltage at serial output pin so v so -0.3 v dd +0.3 v p_4.1.58 current through serial output pin so i so -0.75 0.75 ma p_4.1.45 current through serial output pin so i so -2.0 10.0 ma t 2min. p_4.1.46 temperatures junction temperature t j -40 ? 150 c ? p_4.1.48 storage temperature t stg -55 ? 150 c ? p_4.1.49 esd susceptibility esd susceptibility hbm out pins vs. v s or gnd v esd -4 ? 4 kv 5) hbm p_4.1.50 esd susceptibility hbm other pins v esd -2 ? 2 kv 5) hbm p_4.1.51 table 2 absolute maximum ratings (cont?d) 1) t j = -40 c to +150 c all voltages with respect to ground, positive curr ent flowing into pin (unless otherwise specified) voltage ranges specifed for v s apply also to v s1 and v s2 (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd general product characteristics data sheet 16 rev. 1.0, 2016-06-22 notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. 4.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. esd susceptibility cdm pin 1, 12, 13, 24 (corner pins) v esd -750 ? 750 v 6) cdm p_4.1.52 esd susceptibility cdm v esd -500 ? 500 v 6) cdm p_4.1.54 1) not subject to production test, specified by design. 2) for a duration of t on = 400 ms; t on / t off = 10%; limited to 100 pulses 3) device is mounted on a fr4 2s2p board according to je dec jesd51-2,-5,-7 at natural convection; the product (chip+package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70 m cu, 2 * 35 m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. 4) pulse shape represents inductive switch off: i l (t) = i l (0) x (1 - t / t pulse ); 0 < t < t pulse 5) esd susceptibility, hbm accordin g to ansi/esda/jedec js001 (1.5k ? , 100 pf) 6) esd susceptibility, charged device model ?cdm? esda stm5.3.1 or ansi/esd s.5.3.1 table 3 functional range parameter symbol values unit note / test condition number min. typ. max. supply voltage range for normal operation v s(nor) 7?18v? p_4.2.1 upper supply voltage range for extended operation v s(ext,up) 18 ? 28 v parameter deviation possible p_4.2.2 lower supply voltage range for extended operation v s(ext,low) 3 ? 7 v parameter deviation possible p_4.2.3 junction temperature t j -40 ? 150 c ? p_4.2.4 logic supply voltage v dd 3?5.5v? p_4.2.5 table 2 absolute maximum ratings (cont?d) 1) t j = -40 c to +150 c all voltages with respect to ground, positive curr ent flowing into pin (unless otherwise specified) voltage ranges specifed for v s apply also to v s1 and v s2 (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd general product characteristics data sheet 17 rev. 1.0, 2016-06-22 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . 4.3.1 pcb set up figure 4 2s2p pcb cross section table 4 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to soldering point r thjsp ?57k/w 1) measured to exposed pad (pin 25) 1) not subject to production test, specified by design p_4.3.4 junction to ambient r thja ?32?k/w 1)2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 * 114.3 * 1.5 mm board wit h 2 inner copper layers (2 * 70 m cu, 2 * 35 m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. p_4.3.5 1. 5mm 70m 35m 0.3mm zth_pcb_2s2p.emf
tle75080-emd general product characteristics data sheet 18 rev. 1.0, 2016-06-22 figure 5 pc board for thermal simula tion with 600 mm2 cooling area figure 6 pc board for thermal simu lation with 2s2p cooling area
tle75080-emd general product characteristics data sheet 19 rev. 1.0, 2016-06-22 4.3.2 thermal impedance figure 7 typical thermal impedance. pcb setup according chapter 4.3.1 figure 8 typical thermal resistance. pcb setup 1s0p 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 zth-ja [k/w] tamb = 105c time [s] 8 channels high side 2s2p 1s0p - 600 mm2 1s0p - 300 mm2 1s0p - footprint 30.00 40.00 50.00 60.00 70.00 80.00 90.00 100.00 0 100 200 300 400 500 600 700 rth-ja [k/w] area [mm2] 8 channels high side 1s0p - tamb = 105c
tle75080-emd control pins data sheet 20 rev. 1.0, 2016-06-22 5 control pins the device has three pins (in0, in1 and idle) to control directly the device without using spi. 5.1 input pins tle75080-emd has two input pins available. each input pin is connected by defaul t to one channel (in0 to channel 2, in1 to channel 3). input mapping registers mapin0 and mapin1 can be programmed to connect additional or different channels to each input pin, as shown in figure 9 . the signals driving the channels are an or combination between out register status, in0 and in1 (accordin g to input mapping registers status). figure 9 input mapping the logic level of the input pins can be moni tored via the input status monitor register ( inst ). the input status monitor is operative also when tle75080-emd is in limp home mode. if one of the input pins is set to ?high? and the idle pin is set to ?low?, the device switches in to limp home mode and activates the channel mapped by default to the input pins. see chapter 6.1.5 for further details. 5.2 idle pin the idle pin is used to bring the device into sleep mode operation when is set to ?low? and all input pins are set to ?low?.when idle pin is set to ?low? while one of the in put pins is set to ?high? the device enters limp home mode. to ensure a proper mode transition, idle pin must be set for at least t idle2sleep (p_6.3.54, transition from ?high? to ?low?) or t sleep2idle (p_6.3.53, tran sition from ?low? to ?high?). setting the idle pin to ?low? has the following consequences: ? all registers in the spi are reset to default values ? v dd and v s undervoltage detection circuits are disabled to decrease current consumption (if both inputs are set to ?low?) ? no spi communication is allowed (so pin remains in hi gh impedance state also when csn pin is set to ?low?) if both input pins are set to ?low? inputmapping _8ch.emf channel 7 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 channel 0 or & in1 i in 1 in0 i in 0 & mapin1 mapin0 out or 8 8 8 8 8 8 8 limp home mode (default ) limp home mode (default )
tle75080-emd control pins data sheet 21 rev. 1.0, 2016-06-22 5.3 electrical charact eristics control pins table 5 electrical characteristics: control pins v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. idle pin l-input level v idle(l) 00.8v? p_5.3.1 h-input level v idle(h) 2.0 5.5 v ? p_5.3.2 l-input current i idle(l) 51220 a v idle = 0.8 v p_5.3.3 h-input current i idle(h) 14 28 45 a v idle = 2.0 v p_5.3.4 input pins l-input level v in(l) 00.8v? p_5.3.5 h-input level v in(h) 2.0 5.5 v ? p_5.3.6 l-input current i in(l) 51220 a v in = 0.8 v p_5.3.7 h-input current i in(h) 14 28 45 a v in = 2.0 v p_5.3.8
tle75080-emd power supply data sheet 22 rev. 1.0, 2016-06-22 6 power supply the tle75080-emd is supplied by four supply voltages: ? v s (analog supply voltage used also for the logic) ? v s1 (analog supply voltage used as drain for channels 0, 2, 4 and 6) ? v s2 (analog supply voltage used as drain for channels 1, 3, 5 and 7) ? v dd (digital supply voltage) the v s supply line is connected to a battery feed and used, in combination with v dd supply, for the driving circuitry of the power stages. in situations where v s voltage drops below v dd voltage (for instance during cranking events down to 3.0 v), an increased current consumption may be observed at vdd pin. v s and v dd supply voltages have an undervoltage detection circ uit, which prevents the acti vation of the associated function in case the measured voltage is belo w the undervoltage threshold. more in detail: ? an undervoltage on both v s and v dd supply voltages prevents the activa tion of the power stages and any spi communication (the spi registers are reset) ? an undervoltage on v dd supply prevents any spi communication. spi read/write registers are reset to default values. ? an undervoltage on v s supply forces the tle75080-emd to drain all needed current for the logic from v dd supply. all channels are disabled, and are enabled again as soon as v s v s(op) . figure 10 shows a basic concept drawing of the interaction between supply pins vs and vdd, the output stage drivers and so supply line. figure 10 tle75080-emd internal power supply concept when 3.0 v v s v dd - v sdiff tle75080-emd operates in ?cranking op erative range? (cor). in this condition the current consumption from vdd pin increases while it decreases from vs pin where the total current consumption remains within the specified limits. figure 11 shows the voltage levels at vs pin where the device goes in and out of cor. during the tran sition to and from cor operative region, i vs and i vdd change between values defined for normal operation and for cor operation. the sum of both current re mains within limits specified in ?overall current cons umption? section (see table 8 ). cp gd ch. 0,2,4,6 vs1 supplyconcept_8hs.emf vs vdd i vs i vdd vreg spi so uvr vdd uvr vs gd ch. 1,3,5,7 vs2 hs hs
tle75080-emd power supply data sheet 23 rev. 1.0, 2016-06-22 figure 11 ?cranking operative range? furthermore, when v s(uv) v s v s(op) it may be not possible to switch on a channel that was previously off. all channels that are already on keep their state unle ss they are switched off via spi or via inn pins. an overview of channel behavior according to different v s and v dd supply voltages is shown in table 6 (the table is valid after a successful power-up, see chapter 6.1.1 for more details). supply transition supply transition supplyconcept_cor.emf t v s v dd + v sd iff v dd -v sd iff 3.0 v (no ) cor yes (no) t i vs v dd i vd d t
tle75080-emd power supply data sheet 24 rev. 1.0, 2016-06-22 table 6 device capability as function of v s and v dd v dd v dd(uv) ( v dd(uv) = p_6.3.25) v dd = v dd(lop) ( v dd(lop) = p_6.3.24) v dd > v dd(lop) v s 3.0 v 3.0 v = v s(uv),max (p_6.3.1) channels cannot be controlled channels cannot be controlled channels cannot be controlled spi registers reset spi registers available spi registers available spi communication not available ( f sclk = 0 mhz) spi communication possible ( f sclk = 1 mhz) (p_10.4.34) spi communication possible ( f sclk = 5 mhz) (p_10.4.22) limp home mode not available limp home mode available (channels are off) limp home mode available (channels are off) 3.0 v < v s v s(op) ( v s(op) = p_6.3.2) channels cannot be controlled by spi channels can be switched on and off (spi control) 1) ( r ds(on) deviations possible) channels can be switched on and off (spi control) 1) ( r ds(on) deviations possible) spi registers reset spi registers available spi registers available spi communication not available ( f sclk = 0 mhz) spi communication possible ( f sclk = 1 mhz) (p_10.4.34) spi communication possible ( f sclk = 5 mhz) (p_10.4.22) limp home mode available 1) ( r ds(on) deviations possible) 1) undervoltage condition on v s must be considered - see chapter 6.2.1 for more details limp home mode available 1) ( r ds(on) deviations possible) limp home mode available 1) ( r ds(on) deviations possible) v s v s(op) channels cannot be controlled by spi channels can be switched on and off (small r ds(on) dev. possible when v s = v s(ext,low) ) channels can be switched on and off (small r ds(on) dev. possible when v s = v s(ext,low) ) spi registers reset spi registers available spi registers available spi communication not available ( f sclk = 0 mhz) spi communication possible ( f sclk = 5 mhz) (p_10.4.22) spi communication possible ( f sclk = 5 mhz) (p_10.4.22) limp home mode available (small r ds(on) dev. possible when v s = v s(ext,low) ) limp home mode available (small r ds(on) dev. possible when v s = v s(ext,low) ) limp home mode available (small r ds(on) dev. possible when v s = v s(ext,low) )
tle75080-emd power supply data sheet 25 rev. 1.0, 2016-06-22 6.1 operation modes tle75080-emd has the following operation modes: ? sleep mode ? idle mode ? active mode ? limp home mode the transition between operation modes is determined according to following levels and states: ? logic level at idle pin ? logic level at inn pins ? out.outn bits state ? hwcr.act bit state the state diagram including the possible transitions is shown in figure 12 . the behaviour of tle75080-emd as well as some parameters may change in dependence from the operation mode of the device. furthermore, due to the undervoltage detection circuitry which monitors v s and v dd supply voltages, some changes within the same operation mode can be seen accordingly. the operation mode of the tle75080-emd can be observed by: ? status of output channels ? status of spi registers ? current consumption at vdd pin ( i vdd ) ? current consumption at vs pin ( i vs ) the default operation mode to switch on the loads is active mode. if the device is not in active mode and a request to switch on one or more ou tputs comes (via spi or via input pins), it will switch into active or limp home mode, according to idle pin status. due to the time needed for such transitions, output turn-on time t on will be extended due to the mode transition latency. figure 12 operation mode state diagram opmodes.emf sleep idle idle = ?high? idle = ?low? active inn = ?high? & idle = ?lo w? idle = ?high? limp home hwcr.act = 1 or out.out n = 1 or inn = ?high? hwcr.act = 0 & out.out n = 0 & inn = ?lo w? idle = ?low? & inn = ?high ? inn = ?low? init idle = ?low? & inn = ?low? inn = ?low? & v dd < v dd(uv)
tle75080-emd power supply data sheet 26 rev. 1.0, 2016-06-22 table 7 shows the correlation betwee n device operation modes, v s and v dd supply voltages, and state of the most important functions (channels operativity, spi communication and spi registers). 6.1.1 power-up the power-up condition is satisfied when one of the supply voltages ( v s or v dd ) is applied to the device and the inn or idle pins are set to ?high?. if v s is above the threshold v s(op) or if v dd is above the threshold v dd(lop) the internal power-on signal is set. 6.1.2 sleep mode when tle75080-emd is in sleep mode, all outputs ar e off and the spi registers are reset, independently from the supply voltages. the current cons umption is minimum. see parameters i vdd(sleep) and i vs(sleep) , or parameter i sleep for the whole device. 6.1.3 idle mode in idle mode, the current consumption of the de vice can reach the limits given by parameters i vdd(idle) and i vs(idle) , or by parameter i idle for the whole device. the internal voltage regu lator is working. diagnosis functions are not available. the output channels are switched off, independently from the supply voltages. when v dd is available, the spi registers are working and spi communi cation is possible. in idle mode the errn bits are not cleared for functional safety reasons. 6.1.4 active mode active mode is the normal operation mode of tle75080 -emd when no limp home condition is set and it is necessary to drive some or all loads. voltage levels of v dd and v s influence the behavior as described at the beginning of chapter 6 . device current consumption is specified with i vdd(active) and i vs(active) ( i active for the table 7 device function in relation to operation modes, v s and v dd voltages operation mode function undervoltage condition on v s 1) v dd v dd(uv) 1) see chapter 6.2.1 for more details undervoltage condition on v s v dd > v dd(uv) v s not in undervoltage v dd v dd(uv) v s not in undervoltage v dd > v dd(uv) sleep channels not available not available not available not available spi comm. not available not available not available not available spi registers reset reset reset reset idle channels not available not available not available not available spi comm. not available ? not available ? spi registers reset ? reset ? active channels not available not available ? (in pins only) ? spi comm. not available ? not available ? spi registers reset ? reset ? limp home channels not available not available ? (in pins only) ? (in pins only) spi comm. not available ? (read-only) not available ? (read-only) spi registers reset ? (read-only) 2) 2) see chapter 6.1.5 for a detailed overview reset ? (read-only) 2)
tle75080-emd power supply data sheet 27 rev. 1.0, 2016-06-22 whole device). the device enters active mode when idle pin is set to ?high? and one of the input pins is set to ?high? or one out.outn bit is set to ?1?. if hwcr.act is set to ?0?, the device return s to idle mode as soon as all inputs pins are set to ?low? and out.outn bits are set to ?0?. if hwcr.act is set to ?1?, the device remains in active mode independently of the status of input pins and out.outn bits. an undervoltage condition on v dd supply brings the device into idle m ode, if all input pins are set to ?low?. even if the registers mapin0 and mapin1 are both set to ?00 h ? but one of the input pins inn is set to ?high?, the device goes into active mode. 6.1.5 limp home mode tle75080-emd enters limp home mode when idle pin is ?low? and one of the input pins is set to ?high?, switching on the channel connec ted to it. spi communication is possible bu t only in read-only mode (spi registers can be read but cannot be written). more in detail: ? uvrvs and lopvdd are set to ?1? ? mode bits are set to ?01 b ? (limp home mode) ? ter bit is set to ?1? on the first spi command after entering limp home mode. afterwards it works normally ? oloff bits is set to ?0? ? errn bits work normally ? diag_osm.outn bits can be read and work normally ? all other registers are set to their default value and ca nnot be programmed as long as the device is in limp home mode see table 6 for a detailed overview of supply voltage conditio ns required to switch on channels 2 and 3 during limp home. all other channels are off. a transmission of spi commands during transition from active to limp home mode or limp home to active mode may result in undefined spi responses. 6.1.6 definition of power su pply modes transition times the channel turn-on time is as defined by parameter t on when tle75080-emd is in active mode or in limp home mode. in all other cases, it is necessary to add the tran sition time required to reach one of the two aforementioned power supply modes (as shown in figure 13 ).
tle75080-emd power supply data sheet 28 rev. 1.0, 2016-06-22 figure 13 transition time diagram 6.2 reset condition one of the following 3 conditions resets the spi registers to the default value: ? v dd is not present or below the undervoltage threshold v dd(uv) ? idle pin is set to ?low? ? a reset command ( hwcr.rst set to ?1?) is executed ? errn bits are not cleared by a reset command (for functional safety) ? uvrvs and lopvdd bits are cleared by a reset command in particular, all channels are switched off (if there are no input pin set to ?high?) and the input mapping configuration is reset. 6.2.1 undervoltage on v s between v s(uv) and v s(op) the undervoltage mechanism is triggered. if the device is operative and the supply voltage drops below the undervoltage threshold v s(uv) , the logic set the bit uvrvs to ?1?. as soon as the supply voltage vs is above the minimu m voltage operative threshold v s(op) , the bit uvrvs is set to ?0? after the first standard diagnosis readout. undervolta ge condition on vs influences the st atus of the channels, as described in table 6 . figure 14 sketches the undervoltage behavior (the ? v s - v ds ? line refers to a channel which is programmed to be on). opmodestimings.emf sleep idle t sleep2idle active limp home init t idle2sleep t active2idle t idle2active t on t active2lh t lh2active t lh2sleep t sleep2lh t on channel on t active2sleep
tle75080-emd power supply data sheet 29 rev. 1.0, 2016-06-22 figure 14 v s undervoltage behavior 6.2.2 low operating power on v dd when v dd supply voltage is in the range indicated by v dd(lop) , the bit lopvdd is set to ?1?. as soon as v dd > v dd(lop) the bit lopvdd is set to ?0? after the firs t standard diagnosis readout. if v dd supply voltage is not present, a voltage applied to pins csn or so can supply the internal logic (not recommended in normal operation due to internal design limitations). supply_uvrvs.emf t v s(op) v s(uv) 1 uvrvs 0 1 t v s(hys) t v s - v ds v s
tle75080-emd power supply data sheet 30 rev. 1.0, 2016-06-22 6.3 electrical charact eristics power supply table 8 electrical characteristics power supply v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c, all voltages wit h respect to ground, positive currents flowing as described in figure 2 (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. vs pin analog supply undervoltage shutdown v s(uv) 1.5 ? 3.0 v outn = on from v ds 1v to uvrvs = 1 b r l = 50 ? p_6.3.1 analog supply minimum operative voltage v s(op) ??4.0v out.outn = 1 b from uvrvs = 1 b to v ds 1v r l = 50 ? p_6.3.2 undervoltage shutdown hysteresis v s(hys) ?1?v 1) p_6.3.3 analog supply current consumption in sleep mode with loads i vs(sleep) ?0.13a 1) v idle floating v inn floating v csn = v dd t j 85 c p_6.3.4 analog supply current consumption in sleep mode with loads i vs(sleep) ?0.1?a 1) v idle floating v inn floating v csn = v dd t j 85 c vs = 13.5 v p_6.3.63 analog supply current consumption in sleep mode with loads i vs(sleep) ?0.120a v idle floating v inn floating v csn = v dd t j = 150 c p_6.3.5 analog supply current consumption in idle mode with loads i vs(idle) ? ? 2.2 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 0 b out.outn = 0 b diag_iol.outn = 0 b v csn = v dd p_6.3.6
tle75080-emd power supply data sheet 31 rev. 1.0, 2016-06-22 analog supply current consumption in idle mode with loads (cor) i vs(idle) ? ? 0.3 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 0 b out.outn = 0 b diag_iol.outn = 0 b v csn = v dd v s v dd - 1 v p_6.3.7 analog supply current consumption in active mode with loads - channels off i vs(active) ? ? 7.7 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 0 b diag_iol.outn = 0 b v csn = v dd p_6.3.10 analog supply current consumption in active mode with loads - channels off (cor) i vs(active) ? ? 5.0 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 0 b diag_iol.outn = 0 b v csn = v dd v s v dd - 1 v p_6.3.14 analog supply current consumption in active mode with loads - channels on i vs(active) ? ? 7.7 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 1 b diag_iol.outn = 0 b v csn = v dd p_6.3.16 analog supply current consumption in active mode with loads - channels on (cor) i vs(active) ? 2.3 5.0 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 1 b diag_iol.outn = 0 b v csn = v dd v s v dd - 1 v p_6.3.22 table 8 electrical characteristics power supply (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c, all voltages wit h respect to ground, positive currents flowing as described in figure 2 (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd power supply data sheet 32 rev. 1.0, 2016-06-22 vdd pin logic supply operating voltage v dd(op) 3.0 ? 5.5 v f sclk = 5 mhz p_6.3.23 logic supply lower operating voltage v dd(lop) 3.0 ? 4.5 v ? p_6.3.24 undervoltage shutdown v dd(uv) 1?3.0v v si = 0 v v sclk = 0 v v csn = 0 v so from ?low? to high impedance p_6.3.25 logic supply current in sleep mode i vdd(sleep) ?0.12.5a 1) v idle floating v inn floating v csn = v dd t j 85 c p_6.3.26 logic supply current in sleep mode i vdd(sleep) ??10a v idle floating v inn floating v csn = v dd t j = 150 c p_6.3.27 logic supply current in idle mode i vdd(idle) ? ? 0.3 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 0 b out.outn = 0 b v csn = v dd p_6.3.28 logic supply current in idle mode (cor) i vdd(idle) ? ? 2.2 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 0 b out.outn = 0 b v csn = v dd v s v dd - 1 v p_6.3.29 logic supply current in active mode - channels off i vdd(active) ? ? 0.3 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 0 b v csn = v dd p_6.3.30 table 8 electrical characteristics power supply (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c, all voltages wit h respect to ground, positive currents flowing as described in figure 2 (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd power supply data sheet 33 rev. 1.0, 2016-06-22 logic supply current in active mode - channels off (cor) i vdd(active) ? ? 2.7 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 0 b v csn = v dd v s v dd - 1 v p_6.3.33 logic supply current in active mode - channels on i vdd(active) ? ? 0.3 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 1 v csn = v dd p_6.3.35 logic supply current in active mode - channels on (cor) i vdd(active) ? ? 3.5 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 1 b diag_iol.outn = 0 b v csn = v dd v s v dd - 1 v p_6.3.66 overall current consumption overall current consumption in sleep mode i vs(sleep) + i vdd(sleep) i sleep ??5a 1) v idle floating v inn floating v csn = v dd t j 85 c p_6.3.40 overall current consumption in sleep mode i vs(sleep) + i vdd(sleep) i sleep ??5a 1) v idle floating v inn floating v csn = v dd t j 85 c v s = 13.5 v p_6.3.64 overall current consumption in sleep mode i vs(sleep) + i vdd(sleep) i sleep ??30a v idle floating v inn floating v csn = v dd t j = 150 c p_6.3.41 table 8 electrical characteristics power supply (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c, all voltages wit h respect to ground, positive currents flowing as described in figure 2 (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd power supply data sheet 34 rev. 1.0, 2016-06-22 overall current consumption in idle mode i vs(idle) + i vdd(idle) i idle ? ? 2.5 ma idle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 0 b out.outn = 0 b diag_iol.outn = 0 b v csn = v dd p_6.3.42 overall current consumption in active mode - channels off i vs(active) + i vdd(active) i active ??8maidle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 0 b diag_iol.outn = 0 b v csn = v dd p_6.3.45 overall current consumption in active mode - channels on i vs(active) + i vdd(active) i active ??8maidle = ?high? v inn floating f sclk = 0 mhz hwcr.act = 1 b out.outn = 1 b diag_iol.outn = 0 b v csn = v dd p_6.3.50 voltage difference between v s and v dd supply lines v sdiff ?200?mv 1) p_6.3.52 timings sleep to idle delay t sleep2idle ? 200 400 s 1) from idle pin to ter + inst register = 8680 h (see chapter 10.6.1 for details) p_6.3.53 idle to sleep delay t idle2sleep ? 100 200 s 1) from idle pin to standard diagnosis = 0000 h (see chapter 10.5 for details) external pull-down so to gnd required p_6.3.54 table 8 electrical characteristics power supply (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c, all voltages wit h respect to ground, positive currents flowing as described in figure 2 (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd power supply data sheet 35 rev. 1.0, 2016-06-22 idle to active delay t idle2active ? 100 200 s 1) from inn or csn pins to mode = 10 b p_6.3.55 active to idle delay t active2idle ? 100 200 s 1) from inn or csn pins to mode = 11 b p_6.3.56 sleep to limp home delay t sleep2lh ?300 + t on 600 + t on s 1) from inn pins to v ds = 10% v s p_6.3.57 limp home to sleep delay t lh2sleep ?200 + t off 400 + t off s 1) from inn pins to standard diagnosis = 0000 h (see chapter 10.6.1 for details). external pull-down so to gnd required p_6.3.58 limp home to active delay t lh2active ?50100s 1) from idle pin to mode = 10 b p_6.3.59 active to limp home delay t active2lh ?50100s 1) from idle pin to ter + inst register = 8683 h (in0 = in1 = ?high?) or 8682 h (in1 = ?high?, in0 = ?low?) or 8681 h (in1 = ?low?, in0 = ?high?) (see chapter 10.5 for details) p_6.3.60 active to sleep delay t active2sleep ?50100s 1) from idle pin to standard diagnosis = 0000 h (see chapter 10.6.1 for details). external pull-down so to gnd required. p_6.3.61 1) not subject to production test - specified by design table 8 electrical characteristics power supply (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c, all voltages wit h respect to ground, positive currents flowing as described in figure 2 (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd power stages data sheet 36 rev. 1.0, 2016-06-22 7 power stages the tle75080-emd is an eight channels high-side relay switch. the power stages are built by n-channel lateral power mosfet transistors. the supply voltages v s1 and v s2 can be connected to any potential between ground and v s . a charge pump is connected to the output mosfet gate. 7.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage as well as the junction temperature t j . 7.1.1 switching resistive loads when switching resistive loads the following s witching times and slew rates can be considered. figure 15 switching a resistive load 7.1.2 inductive output clamp when switching off inductive loads, the voltage across the power switch rises to v ds(cl) potential, because the inductance intends to continue driving the current. the potential at output pin is not allowed to go below v out(cl) . the voltage clamping is necessary to prevent device destruction. figure 16 shows a concept drawing of the implementation. nevertheless, the maximum allowed load inductance is limited. the clamping structure protects the device in all operative modes (sleep, idle, active, limp home). v ds t swit ch on . e m f t on t off t 90% of v s d v / d t on 70% d v / d t off 30% t delay(on) t delay(off) inn / out.outn 70% of v s 30% of v s 10% of v s
tle75080-emd power stages data sheet 37 rev. 1.0, 2016-06-22 figure 16 output clamp concept 7.1.3 maximum load inductance during demagnetization of induct ive loads, energy has to be dissipated in the tle75080-emd. equation (7.1) and equation (7.2) can be used for high-side switches : (7.1) (7.2) the maximum energy, which is converted into heat, is limited by the thermal design of the component. the e ar value provided in table 2 assumes that all channels can dissipate the same energy when the inductances connected to the outputs are demagnetized at the same time. 7.2 inverse current behavior during inverse current ( v outn > v sn ) the affected channels stays in on- or in off- state. furthermore, during applied inverse currents the errn bit can be set if the channel is in on -state and the over temperature threshold is reached. the general functionality (switch on a nd off, protection, diagno stic) of unaffected channels is not influenced by inverse currents applied to other channels. parameter de viations are possible especially for the following ones (over temperature protection is not influenced): ? switching capability: t on , t off , dv/dt on , - dv/dt off ? protection: i l(ovl0) , i l(ovl1) ? diagnostic: v out(ol) reliability in limp home condition for the unaffecte d channels is unchanged. note: no protection mechanism like temper ature protection or over load protection is active during applied inverse currents. inverse currents cause power losses inside the dmos, which increase the overall device temperature. this could lead to a switch off of unaffected channels due to over temperature po we rsta g e_ hs.e m f high-side channel v s l , r l v outn i l_ s v out(cl) v ds(cl) i l vsn outn v ds gnd ev s v ? outs cl () () v outs cl () r l ------------ -------------- - 1 r l i ? l v outs cl () ------------- ------------- - ? ?? ?? i l + ln ? l r l ------ ?? = ev s v ? out cl () () v out cl () r l ------------ ----------- - 1 r l i ? l v out cl () ------------- ---------- - ? ?? ?? i l + ln ? l r l ------ ?? =
tle75080-emd power stages data sheet 38 rev. 1.0, 2016-06-22 7.3 switching channels in parallel in case of appearance of a short circuit with channels in parallel, it may happen that the two channels switch off asynchronously, therefore bringing an additional thermal stress to the channel that s witches off last. in order to avoid this condition, it is possible to parametrize in the spi registers the parallel operation of two neighbour channels (bits hwcr.par ). when operating in this mode, the fastest channel to react to an over load or over temperature conditi on will deactivate also the othe r. the inductive energy that two channels can handle once set in parallel is lower than twice the single channel energy (see p_7.6.11). it is possible to synchronize the following couples of channels: ? channel 0 and channel 2 hwcr.par (0) set to ?1? ? channel 1 and channel 3 hwcr.par (1) set to ?1? ? channel 4 and channel 6 hwcr.par (2) set to ?1? ? channel 5 and channel 7 hwcr.par (3) set to ?1? the synchronization bits influence onl y how the channels react to over l oad or over temperature conditions. synchronized channels have to be switched on and off individually by the micro-controller.
tle75080-emd power stages data sheet 39 rev. 1.0, 2016-06-22 7.4 electrical charact eristics power stages table 9 electrical characteristics: power stage v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. output characteristics on-state resistance r ds(on) ?1.0? ? 1) t j = 25 c p_7.6.1 on-state resistance r ds(on) ?1.82.2 ? t j = 150 c i l = i l(ear) = 220 ma p_7.6.2 nominal load current (all channels active) i l(nom) ? 330 500 2)3) ma 1) t a = 85 c t j 150 c p_7.6.3 nominal load current (all channels active) i l(nom) ? 260 500 2)3) ma 1) t a = 105 c t j 150 c p_7.6.4 nominal load current (half of channels active) i l(nom) ? 470 500 2)3) ma 1) t a = 85 c t j 150 c p_7.6.5 load current for maximum energy dissipation - repetitive (all channels active) i l(ear) ?220?ma 1) t a = 85 c t j 150 c p_7.6.8 inverse current capability per channel - i l(ic) ?? i l(ear) ma 1) no influences on switching functionality of unaffected channels - parameter deviations possible p_7.6.9 maximum energy dissipation repetitive pulses - 2* i l(ear) (two channels in parallel) e ar ??15mj 1) t j(0) = 85 c i l(0) = 2* i l(ear) 2*10 6 cycles hwcr.par = ?1? for affected channels p_7.6.11 power stage voltage drop at low battery v ds(op) ??1v r l = 50 ? v s = v s(op),max v s1 = v s(op),max v s2 = v s(op),max refer to figure 16 p_7.6.15 drain to source output clamping voltage v ds(cl) 42 46 55 v i l = 20 ma v s = v sn = 36 v p_7.6.16
tle75080-emd power stages data sheet 40 rev. 1.0, 2016-06-22 source to ground output clamping voltage v out(cl) -25 ? -16 v i l = 20 ma v s = v sn = 7 v p_7.6.18 output leakage current (each channel) t j 85 c i l(off) ?0.010.5a 1) v in = 0 v or floating v ds = 28 v v out_s = 1.5v out.outn = 0 t j 85 c p_7.6.47 output leakage current (each channel) t j = 150 c i l(off) ?0.15a 1) v in = 0 v or floating v ds = 28 v v out_s = 1.5v out.outn = 0 t j = 150 c p_7.6.49 timings turn-on delay (from inn pin or bit to v out = 10% v s ) t delay(on) 148s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.35 turn-off delay (from inn pin or bit to v out = 90% v s ) t delay(off) 1612s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.36 turn-on time (from inn pin or bit to v out = 90% v s ) t on 61535s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.37 turn-off time (from inn pin or bit to v out = 10% v s ) t off 61535s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.38 turn-on/off matching t on - t off -10 0 10 s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.39 turn-on slew rate v ds = 30% to 70% v s dv/dt on 0.7 1.3 1.9 v/s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.40 table 9 electrical characteristics: power stage (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd power stages data sheet 41 rev. 1.0, 2016-06-22 turn-off slew rate v ds = 70% to 30% v s - dv/dt off 0.7 1.3 1.9 v/s r l = 50 ? v s = 13.5 v active mode or limp home mode p_7.6.41 internal reference frequency synchronization time t sync ?510s 1) p_7.6.45 1) not subject to production test - specified by design 2) if one channel has i l(nom),max applied, the remaining channels must be underloaded accordingly so that t j < 150c 3) i l(nom),max can reach i l(ovl1),min table 9 electrical characteristics: power stage (cont?d) v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd protection functions data sheet 42 rev. 1.0, 2016-06-22 8 protection functions 8.1 over load protection the tle75080-emd is protected in case of over load or short circuit of the load. there are two over load current thresholds (see figure 17 ): ? i l(ovl0) between channel switch on and t ovlin ? i l(ovl1) after t ovlin every time the channel is switch ed off for a time longer than 2 * t sync the over load current threshold is set back to i l(ovl0) . figure 17 over load current thresholds in case the load current is higher than i l(ovl0) or i l(ovl1) , after time t off(ovl) the over loaded channel is switched off and the according diagnosis bit errn is set. the channel can be switched on after clearing the protection latch by setting the corresponding hwcr_ocl.outn bit to ?1?. this bit is set back to ?0? internally after de-latching the channel. please refer to figure 18 for details. figure 18 latch off at over load 8.2 over temperature protection a temperature sensor is integrated for each channel, c ausing an overheated channel to switch off to prevent destruction. the according diagnosis bit errn is set (combined with over load protection). the channel can be inn i l(ovl) t t overloadstep.emf t ovlin out.outn i l(ovl0) i l(ovl 1) inn i ln t t overload.emf t off(ovl) i l(ovln) out.outn spi command to set hwcr_ocl.outn = 1 b t t errn 1 0 0 t 1 0 0 hwcr_ocl.outn
tle75080-emd protection functions data sheet 43 rev. 1.0, 2016-06-22 switched on after clearing the protecti on latch by setting the corresponding hwcr_ocl.outn bit to ?1?. this bit is set back to ?0? internally after de-latching the channel. 8.3 over temperature and over loa d protection in limp home mode when tle75080-emd is in limp home mode, channels 2 and 3 can be switched on using the input pins. in case of over load, short circuit or over temperature the channels switch off. if the input pins remain ?high?, the channels restart with the following timings: ? 10 ms (first 8 retries) ? 20 ms (following 8 retries) ? 40 ms (following 8 retries) ? 80 ms (as long as the input pin remain s ?high? and the er ror is still present) if at any time the input pin is set to ?low? for longer than 2* t sync , the restart timer is re set. at the next channel activation while in limp home mode the timer starts from 10 ms again. see figure 19 for details. over load current thresholds behave as described in chapter 8.1 . figure 19 restart timer in limp home mode 8.4 reverse polarity protection in reverse polarity (also known as reverse batte ry) condition, high-side channels have reversave? functionality. each esd diode of the logic and supply pi ns contributes to total power dissipation. channels with reversave? functionality are switched on almost with the same r ds(on) (see parameter r ds(rev) ). the reverse current through the channels has to be limited by the connected loads. the current through digital power supply v dd and input pins has to be limited as well (please refer to the absolute maximum ratings listed on chapter 4.1 ). note: no protection mechanism like temperature protection or current limitation is active during reverse polarity. 8.5 over voltage protection in the case of supply voltages between v s(sc) and v s(ld) the output transis tors are still operati onal and follow the input pins or the out register. in addition to the output clamp for inductive loads as described in chapter 7.1.2 , there is a clamp mechanism available for over voltage protection for the logic and all channels, moni toring the voltage between vs and gnd pins ( v s(az) ). in0 in1 i l2 i l3 t t lhrestart.emf t retry0(lh) 10 ms 018 t retry1(lh) 20 ms 1 8 t retry2(lh) 40 m s 1 8 t retry3(lh) 80 ms t retry0(lh) 10 ms 01
tle75080-emd protection functions data sheet 44 rev. 1.0, 2016-06-22 8.6 electrical charact eristics protection table 10 electrical characteristics protection v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. over load over load detection current i l(ovl0) 1.3 1.7 2.3 a t j = -40 c p_8.8.19 over load detection current i l(ovl0) 1.25 1.55 2.3 a 1) t j = 25 c p_8.8.20 over load detection current i l(ovl0) 11.452a t j = 150 c p_8.8.21 over load detection current i l(ovl1) 0.7 0.95 1.3 a t j = -40 c p_8.8.22 over load detection current i l(ovl1) 0.65 0.85 1.3 a 1) t j = 25 c p_8.8.23 over load detection current i l(ovl1) 0.5 0.8 1.25 a t j = 150 c p_8.8.24 over load threshold switch delay time t ovlin 110 170 260 s 1) p_8.8.5 over load shut-down delay time t off(ovl) 4711s 1) p_8.8.26 over temperature and over voltage thermal shut-down temperature t j(sc) 150 175 1) 220 1) c p_8.8.7 over voltage protection v s(az) 42 50 60 v i vs = 10 ma sleep mode p_8.8.8 reverse polarity on-state resistance during reverse polarity (high-side channels ) r ds(rev) ?1.0? ? 1) v s = - v s(rev) i l = i l(ear) t j = 25 c p_8.8.11 on-state resistance during reverse polarity (high-side channels ) r ds(rev) ?1.8? ? 1) v s = - v s(rev) i l = i l(ear) t j = 150 c p_8.8.12 timings restart time in limp home mode t retry0(lh) 71013ms 1) p_8.8.13 restart time in limp home mode t retry1(lh) 14 20 26 ms 1) p_8.8.14 restart time in limp home mode t retry2(lh) 28 40 52 ms 1) p_8.8.15 restart time in limp home mode t retry3(lh) 56 80 104 ms 1) p_8.8.16
tle75080-emd protection functions data sheet 45 rev. 1.0, 2016-06-22 1) not subject to production test - specified by design
tle75080-emd diagnosis data sheet 46 rev. 1.0, 2016-06-22 9 diagnosis the spi of tle75080-emd provides diagnosis information about the device and the load status. each channel diagnosis information is independent from other channels. an error condition on one channel has no influence on the diagnostic of other channels in the device (unless configured to work in parallel, see chapter 7.3 for more details). 9.1 over load and over temperature when either an over load or an over temperature occurs on one channel, the diagnosis bit errn is set accordingly. as described in chapter 8.1 and chapter 8.2 , the channel latches off and must be reactivated setting corresponding hwcr_ocl.outn bit to ?1?. 9.2 output stat us monitor the device compares each channel v out with v out(ol) and sets the corresponding diag_osm.outn bits accordingly. the bits are updated every time diag_osm register is read. ? v out > v out(ol) diag_osm.outn = ?1? a diagnosis current i ol in parallel to the power switch can be enabled by programming the diag_iol.outn bit, which can be used for open load at off detection. ea ch channel has its dedicated diagnosis current source. if the diagnosis current i ol is enabled or if the channel changes state (on off or off on) it is necessary to wait a time t osm for a reliable diagnosis. enabling i ol current sources in creases the current consumption of the device. even if an open load is detec ted, the channel is not latched off. see figure 20 for a timing overview (the values of diag_iol.outn refer to a channel in normal operation properly connected to the load). figure 20 output status monitor timing output status monitor diagn ostic is available when v s = v s(nor) and v dd v dd(uv) . due to the fact that output status monitor checks the volt age level at the outputs in real time, for open load in off diagnostic it is necessary to synchronize the reading of diag_osm register with the off state of the channels. figure 21 shows how output status monitor is implemented at concept level. inn t outstatmon_timings.emf out.outn 1 t t on + t osm diag_osm.outn 0 t x t spi readout of diag_osm.outn 1 0 0 ou tpu t vo lt ag e comp arato r t off + t osm x 0 x x
tle75080-emd diagnosis data sheet 47 rev. 1.0, 2016-06-22 figure 21 output status monitor - concept in standard diagnosis the bit oloff represents the or combination of all diag_osm.outn bits for all channels in off state which have the corresponding current source i ol activated. outstatmon_hs.emf high-side channel gnd v s v outn vsn outn v ds r ol i ol i ol v out(ol) diag_osm.outn v out > v out(ol) ? diag_osm.outn = ?1"
tle75080-emd diagnosis data sheet 48 rev. 1.0, 2016-06-22 9.3 electrical characteristics diagnosis table 11 electrical characteristics diagnosis v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. output status monitor output status monitor comparator settling time t osm ??20s 1) 1) not subject to production test - specified by design p_9.5.1 output status monitor threshold voltage v out(ol) 33.33.6v 2) 2) output status detection voltages are referenced to ground (gnd pin) p_9.5.3 output diagnosis current i ol 70 85 100 a v out = 3.3 v p_9.5.5 open load equivalent resistance r ol 30 ? 300 k ? 1) p_9.5.6
tle75080-emd serial peripheral interface (spi) data sheet 49 rev. 1.0, 2016-06-22 10 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex sync hronous serial slave interface, which uses four lines: so, si, sclk and csn. data is transferre d by the lines si and so at the rate given by sclk. the falling edge of csn indicates the beginning of an access. da ta is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of csn. a modulo 8/16 counter ensures that data is taken onl y when a multiple of 8 bit has been transferred after the first 16 bits. otherwise a ter bit is asserted. in th is way the interface provides daisy ch ain capability with 16 bit as well as with 8 bit spi devices. figure 22 serial peripheral interface 10.1 spi signal description csn - chip select the system microcontroller selects the tle75080-emd by means of the csn pin. whenever the pin is in ?low? state, data transfer can take place. when csn is in "hig h" state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. csn ?high? to ?low? transition ? the requested information is transferred into the shift register. ? so changes from high impedance state to "high" or ?low? state depending on the logic or combination between the transmission error flag (ter) and the signal level at pin si. this allo ws to detect a faulty transmission even in daisy chain configuration. ? if the device is in sleep mode, so pin remains in high impedance state and no spi transmission occurs. figure 23 combinatorial logic for ter bit 14 13 12 11 14 13 12 11 msb msb spi _16bit.emf lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 10 9 8 10 9 8 7 7 so si csn sclk time spi _ ter. e m f si spi or ter 0 1 so csn scl k s so s si
tle75080-emd serial peripheral interface (spi) data sheet 50 rev. 1.0, 2016-06-22 csn ?low? to "high" transition ? command decoding is only done, when af ter the falling edge of csn exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected after the first 16 sclk pulses. in case of faulty transmission, the transmission error bit ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. sclk - serial clock this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in ?low? state whenever chip select csn makes any transition, otherwise the command may be not accepted. si - serial input serial input data bits are shift-in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the input data consists of two parts, control bits follow ed by data bits. please refer to chapter 10.5 for further information. so serial output data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the csn pin goes to ?low? state. new data appears at the so pin following the rising edge of sclk. please refer to chapter 10.5 for further information. 10.2 daisy chain capability the spi of tle75080-emd provides dais y chain capability. in this configur ation several devices are activated by the same csn signal mcsn. the si line of one device is connected with the so lin e of another device (see figure 24 ), in order to build a chain. the end of the chain is connected to the output and input of the master device, mo and mi respectively. the master dev ice provides the master clock mclk which is connected to the sclk line of each device in the chain. figure 24 daisy chain configuration in the spi block of each device, there is one shift register where each bit from si line is shifted in each sclk. the bit shifted out occurs at the so pin. after sixteen sclk cycl es, the data transfer for one device is finished. in single chip configuration, the csn line must turn ?high? to ma ke the device acknowledge the transferred data. in daisy si device 1 spi sclk so csn si device 2 spi sclk so csn si device 3 spi sclk so csn mo mi mcsn mclk spi_daisychain_1.emf
tle75080-emd serial peripheral interface (spi) data sheet 51 rev. 1.0, 2016-06-22 chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. when using three devices in daisy chain, several multiples of 8 bi ts have to be shifted through the devices (depending on how many devices with 8 bit spi and how many with 16 bit spi). af ter that, the mcsn line must turn ?high? (see figure 25 ). figure 25 data transfer in daisy chain configuration 10.3 timing diagrams figure 26 timing diagram spi access mi mo mcsn mclk si device 3 si device 2 si device 1 so device 3 so device 2 so device 1 spi_daisychain_2.emf csn sclk si t csn(lead) t csn(td) t csn(lag) t sc l k (h ) t sc l k ( l ) t sc l k( p ) t si ( s u) t si (h ) so t so( v ) t so(en) t so (d is ) v csn(h) spi _ tim in g s.e m f v csn(l) v sc l k( h ) v sc l k( l ) v si (h ) v si (l ) v so( h ) v so( l )
tle75080-emd serial peripheral interface (spi) data sheet 52 rev. 1.0, 2016-06-22 10.4 electrical characteristics v dd = 3 v to 5.5 v, v s = 7 v to 18 v, t j = -40 c to +150 c (unless otherwise specified) typical values: v dd = 5 v, v s = 13.5 v, t j = 25 c table 12 electrical characteristics serial peripheral interface (spi) parameter symbol values unit note / test condition number min. typ. max. input characteristics (csn, sclk, si) - ?low? level of pin csn v csn(l) 0?0.8v? p_10.4.1 sclk v sclk(l) 0?0.8v? p_10.4.2 si v si(l) 0?0.8v? p_10.4.3 input characteristics (csn, sclk, si) - ?high? level of pin csn v csn(h) 2? v dd v ? p_10.4.4 sclk v sclk(h) 2? v dd v ? p_10.4.5 si v si(h) 2? v dd v ? p_10.4.6 input pull-up current at pin csn l-input pull-up current at csn pin -i csn(l) 30 60 90 a v dd = 5 v v csn = 0.8 v p_10.4.7 h-input pull-up current at csn pin -i csn(h) 20 40 65 a v dd = 5 v v csn = 2 v p_10.4.8 l-input pull-down current at pin sclk i sclk(l) 51220 a v sclk = 0.8 v p_10.4.9 si i si(l) 51220 a v si = 0.8 v p_10.4.10 h-input pull-down current at pin sclk i sclk(h) 14 28 45 a v sclk = 2 v p_10.4.11 si i si(h) 14 28 45 a v si = 2 v p_10.4.12 output characteristics (so) l level output voltage v so(l) 0?0.4v i so = -1.5 ma p_10.4.13 h level output voltage v so(h) v dd - 0.4 ? v dd v i so = 1.5 ma p_10.4.14 output tristate leakage current i so(off) -1 ? 1 a v csn = v dd v so = 0 v p_10.4.15 output tristate leakage current i so(off) -1 ? 1 a v csn = v dd v so = v dd p_10.4.16 timings enable lead time (falling csn to rising sclk) t csn(lead) 200 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.17 enable lag time (falling sclk to rising csn) t csn(lag) 200 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.18
tle75080-emd serial peripheral interface (spi) data sheet 53 rev. 1.0, 2016-06-22 transfer delay time (rising csn to falling csn) t csn(td) 250 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.19 output enable time (falling csn to so valid) t so(en) ??200ns 1) v dd = 4.5 v or v s > 7 v c l = 20 pf at so pin p_10.4.20 output disable time (rising csn to so tristate) t so(dis) ??200ns 1) v dd = 4.5 v or v s > 7 v c l = 20 pf at so pin p_10.4.21 serial clock frequency f sclk ??5 mhz 1) v dd = 4.5 v or v s > 7 v p_10.4.22 serial clock period t sclk(p) 200 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.23 serial clock ?high? time t sclk(h) 75 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.24 serial clock ?low? time t sclk(l) 75 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.25 data setup time (required time si to falling sclk) t si(su) 20 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.26 data hold time (falling sclk to si) t si(h) 20 ? ? ns 1) v dd = 4.5 v or v s > 7 v p_10.4.27 output data valid time with capacitive load t so(v) ??100ns 1) v dd = 4.5 v or v s > 7 v c l = 20 pf at so pin p_10.4.28 enable lead time (falling csn to rising sclk) t csn(lead) 1?? s 1) v dd = v s = 3.0 v p_10.4.29 enable lag time (falling sclk to rising csn) t csn(lag) 1?? s 1) v dd = v s = 3.0 v p_10.4.30 transfer delay time (rising csn to falling csn) t csn(td) 1.25 ? ? s 1) v dd = v s = 3.0 v p_10.4.31 table 12 electrical characteristics serial peripheral interface (spi) (cont?d) parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd serial peripheral interface (spi) data sheet 54 rev. 1.0, 2016-06-22 output enable time (falling csn to so valid) t so(en) ??1 s 1) v dd = v s = 3.0 v c l = 20 pf at so pin p_10.4.32 output disable time (rising csn to so tristate) t so(dis) ??1 s 1) v dd = v s = 3.0 v c l = 20 pf at so pin p_10.4.33 serial clock frequency f sclk ??1 mhz 1) v dd = v s = 3.0 v p_10.4.34 serial clock period t sclk(p) 1?? s 1) v dd = v s = 3.0 v p_10.4.35 serial clock ?high? time t sclk(h) 375 ? ? ns 1) v dd = v s = 3.0 v p_10.4.36 serial clock ?low? time t sclk(l) 375 ? ? ns 1) v dd = v s = 3.0 v p_10.4.37 data setup time (required time si to falling sclk) t si(su) 100 ? ? ns 1) v dd = v s = 3.0 v p_10.4.38 data hold time (falling sclk to si) t si(h) 100 ? ? ns 1) v dd = v s = 3.0 v p_10.4.39 output data valid time with capacitive load t so(v) ??500ns 1) v dd = v s = 3.0 v c l = 20 pf at so pin p_10.4.40 1) not subject to production test, specified by design table 12 electrical characteristics serial peripheral interface (spi) (cont?d) parameter symbol values unit note / test condition number min. typ. max.
tle75080-emd serial peripheral interface (spi) data sheet 55 rev. 1.0, 2016-06-22 10.5 spi protocol the relationship between si and so content during spi communication is shown in figure 27 . si line represents the frame sent from the c and so line is the answer provided by tle75080-emd. figure 27 relationship between si and so during spi communication the spi protocol provides the answer to a command frame only with the next transmission triggered by the c. although the biggest majority of commands and frames implemented in tle75080-emd can be decoded without the knowledge of what happened before, it is advisable to consider what the c sent in the previous transmission to decode tle75080-emd response frame completely. more in detail, the sequence of commands to ?read? and ?write? the content of a register looks as follows: figure 28 register content sent back to c there are 3 special situations where the frame sent back to the c is not related directly to the previous received frame: ? in case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8 with a minimum of 16 bits), shown in figure 29 ? when tle75080-emd logic supply comes out of power-on reset condition or after a software reset, as shown in figure 30 ? in case of command syntax errors ? ?write? command starting with ?11? instead of ?10? ? ?read? command starting with ?00? instead of ?01? ? ?read? or ?write? commands on registers which are ?reserved? or ?not used? si so frame a frame b (previous response) response to frame a frame c response to frame b spi_si2so.emf si so write register a read register a standard diagnostic register a content (new command ) spi_rwseq.emf (previous response)
tle75080-emd serial peripheral interface (spi) data sheet 56 rev. 1.0, 2016-06-22 figure 29 tle75080-emd response after a error in transmission figure 30 tle75080-emd response after coming out of power-on reset at v dd figure 31 tle75080-emd response after a command syntax error a summary of all possible spi commands is presented in table 13 , including the answer that tle75080-emd sends back at the next transmission. frame a (error in transmission ) spi_so_ter.emf si so (new command) standard diagnostic + ter (previous response ) si so frame a frame b (so = ?z?) frame c response to frame b inst register + ter (8680h) v dd v dd(po) spi _so_ por.emf si so frame a (syntax or addressing error ) (new command) standard diagnostic (previous response ) spi_so _syntaxerro r.emf
tle75080-emd serial peripheral interface (spi) data sheet 57 rev. 1.0, 2016-06-22 table 13 spi command summary 1) 1) ?a? = address bits for addr0 field, ?b? = address bit for addr1 field, ?c? = register content, ?d? = diagnostic bit requested operation frame sent to spider+ (si pin) frame received from spider+ (so pin) with the next command read standard diagnosis 0xxxxxxxxxxxxx01 b (? xxxxxxxxxxxx b ? = dont care) 0ddddddddddddddd b (standard diagnosis) write 8 bit register 10aaaabbcccccccc b where: ? aaaa b ? = register address addr0 ? bb b ? = register address addr1 ? cccccccc b ? = new register content 0ddddddddddddddd b (standard diagnosis) read 8 bit registers 01aaaabbxxxxxx10 b where: ? aaaa b ? = register address addr0 ? bb b ? = register address addr1 ? xxxxxx b ? = dont care 10aaaabbcccccccc b where: ? aaaa b ? = register address addr0 ? bb b ? = register address addr1 ? cccccccc b ? = register content
tle75080-emd serial peripheral interface (spi) data sheet 58 rev. 1.0, 2016-06-22 10.6 spi registers overview 10.6.1 standard diagnosis table 14 standard diagnosis 1514131211109 8 76543210default 0uvr vs lop vdd mode ter 0 ol off err 7800 h field bits type description uvrvs 14 r v s undervoltage monitor 0 b no undervoltage condition on v s detected (see chapter 6.2.1 for more details) 1 b (default) there was at least one v s undervoltage condition since last standard diagnosis readout lopvdd 13 r v dd lower operating range monitor 0 b v dd is above v dd(lop) 1 b (default) there was at least one ? v dd = v dd(lop) ? condition since last standard diagnosis readout mode 12:11 r operative mode monitor 00 b (reserved) 01 b limp home mode 10 b active mode 11 b (default) idle mode ter 10 r transmission error 0 b previous transmission was successful (modulo 16 + n*8 clocks received, where n = 0, 1, 2...) 1 b (default) previous transmission failed the first frame after a reset is ter set to ?high? and the inst register. the second frame is the standard diagnosis with ter set to ?low? (if there was no fail in the previous transmission). oloff 8r open load in off diagnosis 0 b (default) all channels in off state (which have diag_iol.outn bit set to ?1?) have v out_s < v out_s(ol) 1 b at least one channel in off state (with diag_iol.outn bit set to ?1?) has v out_s > v out_s(ol) channels in on state are not considered errn n = 7 to 0 n:0 r over load / over temperature diagnosis of channel n 0 b (default) no failure detected 1 b over temperature or over load
tle75080-emd serial peripheral interface (spi) data sheet 59 rev. 1.0, 2016-06-22 10.6.2 register structure the register banks the digital part have following structure: table 16 summarizes the available registers with their addresing space and size table 15 register structure - all registers 1514131211109876543210default r = 0 w = 1 r = 1 w = 0 addr0 addr1 data xxxx h table 16 register addressing space register name addr0 addr1 size type purpose out n = 7 to 0 0000 b 00 b nr/w power output control register bits out.outn 0 b (default) output is off 1 b output is on mapin0 n = 7 to 0 0001 b 00 b nr/w input mapping (input pin 0) bits mapin0.outn 0 b (default) the output is not connected to the input pin 1 b the output is connected to the input pin note: channel 2 has the corresponding bit set to ?1? by default mapin1 n = 7 to 0 0001 b 01 b nr/w input mapping (input pin 1) bits mapin1.outn 0 b (default) the output is not connected to the input pin 1 b the output is connected to the input pin note: channel 3 has the corresponding bit set to ?1? by default inst 0001 b 10 b 8r input status monitor bit ter 0 b previous transmission was successful (modulo 16 + n*8 clocks received, where n = 0, 1, 2...) 1 b (default) previous transmission failed bits inst.res (6:2) - reserved bits inst.inn (1:0) 0 b (default) the input pin is set to ?low? 1 b the input pin is set to ?high? first register transmitted after a reset of the logic
tle75080-emd serial peripheral interface (spi) data sheet 60 rev. 1.0, 2016-06-22 10.6.3 register summary all registers with addresses not mentioned in table 17 have to be considered as ?reserved?. ?read? operations performed on those registers return the standard diagnosis. the column ?def ault? indicates the content of the register (8 bits) after a reset. diag_iol n = 7 to 0 0010 b 00 b nr/w open load diagnostic current control bits diag_iol.outn 0 b (default) diagnosis current not enabled 1 b diagnosis current enabled diag_osm n = 7 to 0 0010 b 01 b nr output status monitor bits diag_osm.outn 0 b (default) v out_s < v out_s(ol) 1 b v out_s > v out_s(ol) hwcr 0011 b 00 b 8r/w hardware configuration register bit hwcr.act (7) (active mode) 0 b (default) normal operation or device leaves active mode 1 b device enters active mode (see chapter 6.1 for a description of the possible operative mode transitions) bit hwcr.rst (6) (reset) 0 b (default) normal operation 1 b execute reset command (self clearing) bits hwcr.par (3:0) (channels operating in parallel) 0 b (default) normal operation 1 b two neighbour channels have over load and over temperature synchronized (see chapter 7.3 for more details) bits 5:4 - reserved (default: 0 b ) hwcr_ocl n = 7 to 0 0011 b 01 b nw output clear latch bits hwcr_ocl.outn 0 b (default) normal operation 1 b clear the error latch for the selected output table 17 addressable registers 151413-109876543210default r = 0 w = 1 r = 1 w = 0 0000 00 out.outn 00 h r = 0 w = 1 r = 1 w = 0 0001 00 mapin0.outn 04 h table 16 register addressing space (cont?d) register name addr0 addr1 size type purpose
tle75080-emd serial peripheral interface (spi) data sheet 61 rev. 1.0, 2016-06-22 10.6.4 spi command quick list a summary of the most used spi commands (read and write operations on all registers) is shown in table 18 r = 0 w = 1 r = 1 w = 0 0001 01 mapin1.outn 08 h 0 1 0001 10 ter (reserved) inst.inn 00 h r = 0 w = 1 r = 1 w = 0 0010 00 diag_iol.outn 00 h 0 1 0010 01 diag_osm.outn 00 h r = 0 w = 1 r = 1 w = 0 0011 00 hwcr .act hwcr .rst (reserved) hwcr.par 00 h r = 0 w = 1 r = 1 w = 0 0011 01 hwcr_ocl.outn 00 h table 18 spi command quick list register ?read? command? ?write? command content written out 4002 h 80xx h xx h = xxxxxxxx b mapin0 4402 h 84xx h xx h = xxxxxxxx b mapin1 4502 h 85xx h xx h = xxxxxxxx b inst 4602 h n.a. (read-only) ? diag_iol 4802 h 88xx h xx h = xxxxxxxx b diag_osm 4902 h n.a. (read-only) ? hwcr 4c02 h 8cxx h xx h = xxxxxxxx b hwcr_ocl 4d02 h 8dxx h xx h = xxxxxxxx b table 17 addressable registers 151413-109876543210default
tle75080-emd application information data sheet 62 rev. 1.0, 2016-06-22 11 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 32 tle75080-emd application diagram note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. table 19 suggested component values reference value purpose r in 4.7 k ? protection of the micro-controller during over voltage and reverse polarity guarantee tle75080-emd channels off during loss of ground r idle 4.7 k ? protection of the micro-controller during over voltage and reverse polarity guarantee tle75080-emd channels off during loss of ground r csn 500 ? protection of the micro-controller during over voltage and reverse polarity r sclk 500 ? protection of the micro-controller during over voltage and reverse polarity r si 500 ? protection of the micro-controller during over voltage and reverse polarity r so 500 ? protection of the micro-controller during over voltage and reverse polarity r vdd 100 ? logic supply voltage spikes filtering c vdd 100 nf logic supply voltage spikes filtering c vs 68 nf analog supply voltage spikes filtering v ba tt vs out7_hs out5_hs out3_hs out1_hs out6_hs out4_hs out2_hs out0_hs vs1 vs2 v ba tt 1 v ba tt 2 c out c out c out z out 3 c out z out 1 c out c out c out z out 2 c out z out 0 z vs idle in1 so gnd v dd c vd d in0_lh in1_lh li mp ho me r in gp o vdd r in r idle r csn r sclk r si r so si csn vdd scl k in0 gp o gp o gp o gp o gp o gp i gnd application_8hs.emf c vs r vdd r lh r out 7 r out 6
tle75080-emd application information data sheet 63 rev. 1.0, 2016-06-22 11.1 further application information ? please contact us for information regarding the pin fmea ? for further information you may contact http://www.infineon.com/ z vs p6smb30 protection of device during over voltage. zener diode c out 10 nf protection of tle75080-emd against esd and bci table 19 suggested component values (cont?d) reference value purpose
tle75080-emd package outlines data sheet 64 rev. 1.0, 2016-06-22 12 package outlines figure 33 pg-ssop-24-9 package drawing figure 34 tle75080-emd package pads and stencil pg-ssop-24-4, -9-po v01 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 !0.1 c 0.1 a-b 2x 0.65 0.25 2) m c 0.2 d 24x !0.05 a-b b a index marking c (1.47) 1.7 max. 0.08 c seating plane !0.1 3.9 1) 0.35 x 45" ! 0.25 0.64 !0.2 d 6 m 0.2 d +0 -0.1 0.1 stand off +0.06 0.19 8" max. cd 2x 0.1 bottom view 24 1 6.4 !0.25 2.65 13 12 !0.25 pg-ssop-24-4-fp v01 0.45 0.65 1.31 2.65 6.4 5.69
tle75080-emd package outlines data sheet 65 rev. 1.0, 2016-06-22 note: although the package footprint refer to pg-ssop-24 -4, they can be used as reference also the pg-ssop- 24-9 (physical dimensions are the same). green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-fre e soldering according to ipc/jedec j-std-020). for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
tle75080-emd revision history data sheet 66 rev. 1.0, 2016-06-22 13 revision history trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossav e?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?; primarion?, pr imepack?, primestack?, pr o-sil?, profet?, rasic?, reversave?, satric?, si eget?, sindrion?, sipmos?, smartl ewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi allianc e, inc. mips? of mips technologies, inc., u sa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 page or item changes since previous revision all rev. 1.0, 2016-06-22 tle75080-emd datasheet released
edition 2016-06-22 published by infineon technologies ag 81726 munich, germany ? 2016 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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